Linear amplifier using non-linear cmos capacitors

ABSTRACT

The invention provides an amplifier circuit made by digital CMOS processes, the amplifier circuit comprising a main operational amplifier with at least one input and at least one output and a feedback loop including a non-linear gateoxide capacitor, wherein a voltage control means is connected to the main operational amplifier to provide a voltage difference between the output common mode voltage and the input common mode voltage of the main operational amplifier to apply a DC biasing voltage across the non-linear gateoxide capacitor sufficient to operate the non-linear gateoxide capacitor in a bias range where the capacity of the none-linear gateoxide capacitor is almost independent of the applied voltage comprising the bias voltage plus a signal voltage.

[0001] The invention relates to an operational amplifier circuitcomprising a main operational amplifier with at least one input and atleast one output and a feedback loop including a non-linear capacitor.

[0002] Modern receiver architectures for mobile communication do not useIF stages at high frequency but are near-zero-IF circuits. Usually asingle mixer stage shifts the incoming RF signal to a very low frequencyIF at which analogue I and Q signals are then directly converted todigital signals. The digital I and Q signals are passed to a digitalsignal processing circuit to perform the demodulation of the receivedinput signal. The most important analogue circuit block of the describedreceiver architecture is the polyphase filter which acts as channelselection filter. This circuit usually occupies the largest area of thereceiver circuit and is, therefore, critical for the overallperformance. Commercial CMOS realizations of near-zero-IF receivers areso far not available due to penalties imposed by CMOS polyphase filtersin terms of size and performance.

[0003] One of the most critical performance issues is the requiredlinearity of the channel selection filter. Usually, this linearityrequirement requires special analogue process options which allow theproduction of highly linear capacitors. Standard CMOS processes usingsuch analogue process option become more expensive and are no longercompetitive to solutions which avoid analog process options.Furthermore, the analogue process options for CMOS processes haveusually a longer delay due to extra process development time incomparison to baseline CMOS processes. The availability of circuitswhich do not need the analogue process option, supports a short time tomarket.

[0004] The limiting factor for the implementation of analogue filterswith very high linearity in a pure digital CMOS process is therealization of the capacitors. There are in principle three ways forimplementing capacitors in pure digital processes. Either a backendmetal plate capacitor or a MOS capacitor, a gateoxide capacitor or ajunction capacitor, may be used. The metal plate capacitor is highlylinear but has the drawback of a large size which is about eight timesthe size of a gateoxide capacitor. The gateoxide capacitor is muchsmaller but has a non-linear characteristic. The junction capacitoroffers lower capacitor densities than the gateoxide capacitor and has anon-linear characteristic as well.

[0005] There are attempts trying to linearize the gateoxide capacitoreither by using gateoxide capacitors in a parallel or seriesconfiguration. A configuration with two gateoxide capacitors in ananti-parallel arrangement is quite small and has an improved linearityfor zero biasing voltage. However, two capacitors are required. A seriesarrangement of two gateoxide capacitors is somewhat larger but as a goodlinearity if biased for example by means of a diode arranged between thetwo capacitors. However, the series arrangement of two gateoxidecapacitors has the disadvantage of reduced voltage swing and long set uptimes. Therefore, former capacitor realizations result in either toolarge or too non-linear capacitors for telecommunication products.

[0006] In view of the above, it is the object of the invention toprovide an operational amplifier circuit having an excellent linearityin spite of using non-linear capacitors in a feedback loop related to amain operational amplifier included in the operational amplifiercircuit.

[0007] For this purpose, the invention provides an operational amplifiercircuit comprising a main operational amplifier with at least one inputand at least one output and a feedback loop connected to the input andthe outputincluding a non-linear capacitor, wherein a voltage controlmeans is connected to the main operational amplifier to provide avoltage difference between the output common mode voltage and the inputcommon mode voltage of the main operational amplifier to apply a DCbiasing voltage across the non-linear capacitor sufficient to operatethe non-linear capacitor in a bias range where the capacity of thenon-linear capacitor is substantially independent of the applied voltagecomprising the bias voltage plus a signal voltage.

[0008] The operational amplifier circuit of the invention is a new wayto linearize non-linear capacitors, in particular MOS capacitorsavailable in ordinary digital MOS or CMOS processes, to build upcircuits with very high linearity like channel selection filters, e.g.polyphase filters for telecommunication applications. The operationalamplifier circuit of the invention provides an enabling technology tointegrate digital and analogue hardware in future telecommunicationplatforms in a single chip. The operational amplifier circuit of theinvention, furthermore, provides an advantageous way to overcome theabove described problems with non-linear capacitors just by operatingthe capacitors with a biasing voltage such that the non-linearcapacitors are operated in a state where the capacity is almostindependent of the applied signal to be processed. The circuit of theinvention combines the advantage of a small size non-linear capacitorwith the excellent linearity which this circuit shows for comparativelylarge bias voltages which are, for example for gateoxide capacitors,above 1, 2 V.

[0009] The operational amplifier circuits which are constructedaccording to the invention can be used as integrator circuit to build ahigh order active filter. The integrator circuit represents a basicbuilding block for many applications like sigma delta converters,regulators or analog filter banks. It can be used in standard CMOSprocesses where highly linear capacitors are not available.

[0010] According to a preferred embodiment of the invention, thefeedback loop comprises a resistor in parallel to the non-linearcapacitor. The different common mode voltages at the input and theoutput, respectively, of the main operational amplifier results in a DCcurrent through the resistor providing for a biasing voltage across thenon-linear capacitor in a simple and efficient way.

[0011] According to a further preferred embodiment of the invention, thenon-linear capacitor is a MOS transitor or a gateoxide capacitor. Thisallows the non-linear capacitor to be manufactured in a simple MOS orCMOS process with the advantage that the manufacturing of this circuitelement can be integrated in the overall manufacturing process, and thatthere are no special analogue options necessary. A gateoxide capacitoris easier to integrate in the manufacturing process of the overallcircuit and offers high capacitor densities.

[0012] According to a further preferred embodiment of the invention, thea non-linear capacitor is a junction capacitor.

[0013] According to a further preferred embodiment of the invention, thevoltage control means is adapted to provide a preset DC output commonmode voltage to the input of the operational amplifier. The preset DCoutput common mode voltage can thus be appropriately selected to providethe required biasing voltage at the non-linear capacitor.

[0014] According to a further preferred embodiment of the invention, thevoltage control means comprises a voltage regulator for regulating thecommon mode output voltage of the main operational amplifier to thepreset output common mode voltage. Thereby, the common mode outputvoltage of the main operational amplifier is automatically regulated toa voltage value which is preset at the voltage regulator. The voltageregulator is an advantageous solution for adjusting the common modeoutput voltage preferably to VDD/2 which is the most preferred valuebecause this is the operating point of the operational amplifier outputstages which gives the best possible driving capability.

[0015] According to a further preferred embodiment of the invention, thevoltage regulator comprises a regulator operational amplifier to oneinput of which said preset common mode output voltage CM_(out) is fed,and the other input of which regulator operational amplifier isconnected via a first resistor to one output of the main operationalamplifier and via a second resistor to the other output of the mainoperational amplifier, and wherein an output of the regulatoroperational amplifier is connected via a third resistor to one of theinputs of the main operational amplifier and via a fourth resistor toanother input of the main operational amplifier. In this arrangement,the regulator operational amplifier functions to regulate the differenceof the common mode output voltage of the main operational amplifier andthe preset common mode output voltage.

[0016] According to a further preferred embodiment of the invention, thefirst and second resistors have the same resistance value, and whereinthe third and fourth resistors have the same resistance value, wherebythe circuit arrangement is further simplified.

[0017] According to a further preferred embodiment of the invention, thevoltage control means comprise an input stage adapted to provide apreset DC common mode voltage to the input of the operational amplifiercircuit. This input state is an advantageous means to adjust the inputcommon voltage to a level which is close to the supply voltages in aneasy manner. The nodes at the main operational amplifier input representa virtual ground and AC signals at that point are extremely small.

[0018] According to a further preferred embodiment of the invention, theinput stage comprises a CM DC voltage source connected to the inputs ofthe operational amplifier circuit. This is an advantageous way to definethe CM voltage at the input of the operational amplifier circuit.

[0019] According to a further preferred embodiment of the invention,means for setting an internal voltage V_(T) at the input stage of theoperational amplifier circuit are provided. This is an alternative,advantageous way to define the CM voltage at the input of the mainoperational amplifier or the operational amplifier circuit,respectively.

[0020] According to a further preferred embodiment of the invention, theoperational amplifier circuit is made by pure digital CMOS processes. Asstated above, the advantages of the operational amplifier circuit of theinvention are most pronounced when using a pure digital CMOS process forthe manufacture of the semiconductor device as the advantages of a smallsize non-linear capacitor with excellent linearity of the allover deviceare achieved in combination.

[0021] Embodiments of the invention are now described with reference tothe drawings, in which:

[0022]FIG. 1 shows an analogue low pass filter circuit with non-lineargateoxide capacitors as an example of the operational amplifier circuit;

[0023]FIG. 2 is a more detailed circuit diagram of the analogue low passfilter circuit of FIG. 1;

[0024]FIG. 3 is a circuit diagram of the input stage to the filtercircuits of FIGS. 1 and 2;

[0025]FIG. 4 is a analogue low pass filter circuit with two independentamplifiers with chopped input transistor pair;

[0026]FIG. 5 is more detailed circuit diagram of the low pass analoguefilter circuit of FIG. 4; and

[0027]FIG. 6 is a graph showing the relationship between bias voltageand capacity of a non-linear gateoxide capacitor.

[0028] According to FIG. 1, the low pass filter circuit comprises twoinputs IP and IN and two outputs ON and OP. The inputs IP, IN areconnected to a main operational amplifier 2 through input resistors R1_(IN) and R2 _(IN). There are two feedback loops, one from the negativeoutput ON of the main operational amplifier 2 to the positive input IPthereof and another one from the positive output OP of the mainoperational amplifier 2 to the negative input IN thereof. The feedbackloops comprise a feedback resistor R1 _(f) and a capacitor C1 _(f) inthe first mentioned feedback loop 4, and a feedback resistor R2 _(f) anda feedback capacitor C2 _(f) in the second feedback loop 6. The feedbackresistor R1 _(f) and the capacitor C1 _(f) on the one hand and thefeedback resistor R2 _(f) and the feedback capacitor C2 _(f) areconnected in parallel, respectively.

[0029] A voltage control means 8 is connected to the main operationalamplifier 2 to provide a voltage difference between the output commonmode voltage and the input common mode voltage of the main operationalamplifier 2 to apply a DC biasing voltage across the non-lineargateoxide capacitors C1 _(f) and C2 _(f) sufficient to operate thenon-linear gateoxide capacitors C1 _(f) and C2 _(f) in a bias rangewhere the capacity of the gateoxide capacitors C1 _(f), C2 _(f) isalmost independent of the applied voltage comprising the bias voltageplus a signal voltage. The voltage control means 8 is adapted to providea constant DC output common mode voltage to the input of the mainoperational input amplifier 2.

[0030] In the low pass filter circuit of FIG. 1, the voltage controlmeans is put around the main operational amplifier 2 to guarantee afixed DC biasing voltage U_(C)=(U_(C1)+U_(C2))/2 across the gate oxidecapacitors C1 _(f), C2 _(f). This arrangement results in a linearoperation and, furthermore, assures that the gateoxide capacitors C1_(f), C2 _(f) show the largest possible capacitance for a given area.

[0031] The different common mode voltage at the inputs and outputs ofthe main operational amplifier 2 results in a constant DC currentthrough the resistors R1 _(f), R2 _(f). The constant DC biasing voltageU_(C) can be generated in a way which prevents a reduced output voltagearranged for the low pass filter circuit of FIG. 1.

[0032] If the low pass filter circuit of FIG. 1 is cascaded, input andoutput voltage control means with sufficient driving capability toenable the proper DC current through R_(f)/R_(IN) are required. Due tocost reasons, large resistors and small gateoxide capacitors areadvantageously used and lead to small DC currents through R_(f)/R_(IN).

[0033] In order not to reduce the output voltage range for the filtercircuit of FIG. 1, there are two measures necessary to provide aconstant DC biasing voltage U_(C). The first measure is to adjust thecommon mode output voltage to VDD/2 (one half of the supply voltage).This gives the best possible driving capability. The second measure isto adjust the input common voltage to a level which is close to thesupply voltages. The nodes of the main operational amplifier inputrepresent a virtual ground and AC signals at this point are extremelysmall. To implement this circuit principle, the analogue low pass filtercircuit of FIG. 1 can be embodied as shown in FIG. 2.

[0034] The same circuit elements in FIG. 2 have the same referencenumerals as in FIG. 1. The voltage control means 8 of FIG. 1 comprise avoltage regulator 10 for regulating the common mode output voltage ofthe main operational amplifier 2. The voltage regulator comprises aregulator operational amplifier 12 one input of which is fed by a commonmode output voltage CM_(OUT) and the other input of which regulatoroperational amplifier 12 is connected via a first resistor R3 to oneoutput OP of the main operational amplifier 2 and via a second resistorR4 to the other output ON of the main operational amplifier 2. Theoutput of the regulator operational amplifier 12 (OP2) is connected viaa third resistor R5 to one of the inputs IN of the main operationalamplifier 2 and via a forth resistor R6 to another input IP of the mainoperational amplifier 2. The first and second resistors R3, R4 have thesame resistance value, and the third and forth resistors R5, R6 alsohave the same resistance value.

[0035] In the low pass filter circuit of FIG. 2, the differential inputsignal at node pair IN/IP is amplified via the main operationalamplifier 2, and its feedback loops 1A, 1B and is passed on to thedifferential output node pair ON/OP. The differential signal transferfunction is:

U _(out) , diff/U _(IN) , diff=(O _(OP) −U _(ON))/(U _(IP) −U_(IN))=R2/R1*1/(1+JωR2C1).

[0036] The common mode output voltage CM_(out) is set at the invertinginput of the regulator operational amplifier 12. The non-inverting inputof the regulator operational amplifier 12 is connected to the measuredcommon mode output voltage of the main operational amplifier 2 at point14 between the two resistors R3 and R4. If the measured common modeoutput voltage of the main operational amplifier 2 is different fromCM_(out), the regulator operational amplifier 12 produces at its outputa voltage which is fed via R5 and R6 to the inputs of the mainoperational amplifier 2 and adjusts the common mode output voltage ofthe main operational amplifier 2 to CM_(out) (circuit loop IC). The mainoperational amplifier 2 has an inverting common mode transfer function(or limited common mode suppression.). The common mode input voltage ofthe main operational amplifier 2 is set with the resistive networkconsisting of R1 _(IN), R2 _(IN); R1 _(f), R2 _(f) and resistors R5 andR6. The resistors R5, R6 do not determine the differential signaltransfer function.

[0037] The voltage control means 8 of FIG. 1 furthermore comprise aninput stage as shown in FIG. 3 which input stage is adapted to provide apreset DC common mode voltage to the input of the low pass filtercircuit. The input stage 16 comprises a CM, DC voltage source 18connected to the inputs IN, IP of the filter circuit of FIG. 1 or 2,respectively. The input signal is fed to the input stage 16 between theCM, DC voltage source 18 and the inputs IN, IP as indicated by voltagesources 20, 22. The input stage 16 adjusts the input common voltage at alevel close to the supply voltages.

[0038] The main operational amplifier 32 of FIG. 4 consists of a pair ofindependent, symmetric operational amplifiers 32A, 32B with a choppedinput transistors pair as will be described below. The embodiment ofFIG. 4 shows that the concept of putting a voltage control means arounda main operational amplifier 32 is also applicable if the mainoperational amplifier 32 consists of a pair of symmetric amplifiers 32A,32B providing for an excellent linearity of the filter circuit in spiteof the fact that the capacitors C31 _(f), C32 _(f) are gateoxidecapacitors.

[0039]FIG. 5 shows a more detailed circuit diagram of the symmetricoperational amplifiers 32A and 32B of FIG. 4 The filter circuit of FIG.5 comprises two chopped input transistors 50, 52 with chopper switchesS1, S3 related to transistors 50 and chopper switches S2, S4 related totransistors 52. The chopper switches S1-S4 are connected to each otherand to the transistors 50, 52 in a well-known chopper systemarrangement. The source of transistor 50 is connected to ground and thedrain of the transistor 50 is connected through the zero-contact ofchopper switch S3, an amplifier transistor 54 and a current source 56 tosupply voltage. The source of transistor 52 is grounded and the drain oftransistor 52 is connected through the zero-contact of chopper switch S4and amplifier transistor 58 and current source 60 to supply voltage.Node 62 between transistor 64 and current source 56 is connected throughan amplifier 64 to an output stage 66 of amplifier 32A, which outputstage 66 consists of two transistors 68, 70. The output stage 66 againis connected between ground and supply voltage.

[0040] The node 82 between transistor 58 and current source 60 isconnected through an amplifier 84 to an output stage 86 of theoperational amplifier 32B which output stage consists of two transistors88, 90. The output stage 86 again is connected between ground and supplyvoltage.

[0041] In order to embody the feature that the input common voltage isadjusted to a preset level, the sources of the transistors 50, 52 aregrounded, and the internal voltage V_(T) at the input stage of thefilter circuit is set. By means of this circuit arrangement, the saidinput voltage V_(T) and the regulating function of the regulatoroperational amplifier 42 provide for the low cost implementation of thecircuit device and the excellent linearity required for the specificapplication.

[0042]FIG. 6 shows the characteristic of a gateoxide capacitor, i.e. thecapacitance of the capacitor versus a biasing voltage. FIG. 6 shows thatat a bias voltage of >+1,2 V, the capacitance of the capacitor is almostindependent of the voltage applied to it, the voltage including the biasvoltage plus the signal voltage. Therefore, the bias voltage for such aspecific gateoxide capacitor should be somewhat above +1,2 V, e.g. for a0.25 μm CMOS process, in order to use this feature for the purpose ofthe present invention, i.e. to get an excellent linearity of an analoguefilter circuit in spite of the fact of the dependency of the capacitanceof the capacitor from the bias voltage. It is to be noted that FIG. 6shows a characteristic curve for a particular gateoxide capacitor, andthat the absolute values of the bias voltage and the capacity may changefrom one gateoxide capacitor to another type of gateoxide capacitor, butthe general behavior of the capacitors are the same.

1. Amplifier circuit comprising a main amplifier with at least one inputand at least one output and a feedback loop connected to the input andthe output including a non-linear capacitor, wherein a voltage controlmeans is connected to the main amplifier to provide a voltage differencebetween the output common mode voltage and the input common mode voltageof the main amplifier to apply a DC biasing voltage across thenon-linear capacitor to operate the non-linear capacitor in a bias rangewhere the capacity of the non-linear capacitor is substantiallyindependent of the applied voltage comprising the bias voltage plus asignal voltage.
 2. The circuit of claim 1, wherein the feedback loopcomprises a resistor in parallel to the non-linear capacitor.
 3. Thecircuit of claim 1, wherein the non-linear capacitor is a MOS transitoror a gateoxide capacitor.
 4. The circuit of claim 1, wherein thenon-linear capacitor is a juntion capacitor.
 5. The circuit of claim 1,wherein the voltage control means is adapted to provide a constant DCoutput common mode voltage to the input of the amplifier.
 6. The circuitof claim 1 or 5, wherein the voltage control means comprises a voltageregulator for regulating the common mode output voltage of the mainamplifier to the preset output common mode voltage.
 7. The circuit ofclaim 6, wherein the voltage regulator comprises a regulator operationalamplifier one input of which is fed by a said common mode output voltageCM_(out), and the other input of which regulator operational amplifieris connected via a first resistor to one output of the main operationalamplifier and via a second resistor to the other output of the mainoperational amplifier, and wherein an output of the regulatoroperational amplifier is connected via a third resistor to one of theinputs of the main amplifier and via a fourth resistor to another inputof the main amplifier.
 8. The circuit of claim 7, wherein the first andsecond resistors have the same resistance value, and wherein the thirdand fourth resistors have the same resistance value.
 9. The circuit ofclaim 1, wherein the voltage control means comprises an input stageadapted to provide a constant DC common mode voltage to the input of themain amplifier circuit.
 10. The circuit of claim 9, wherein the inputstage comprises a CM, DC voltage source connected to the inputs of themain amplifier circuit.
 11. The circuit of claim 9, comprising means forsetting an internal voltage VT at the input stage of the main amplifiercircuit.
 12. The circuit of any of the preceding claims, wherein themain amplifier circuit is made by digital CMOS processes.